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sy89295u 2.5v/3.3v 1.5ghz precision lvpecl programmable delay precision edge is a register ed trademark of micrel, inc micro leadframe and mlf are registered trademarks of amkor, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com general description the sy89295u is a programmable delay line that delays the input signal using a digital control signal. the delay can vary from 3.2ns to 14.8ns in 10ps increments. in addition, the input signal is lvpecl, uses either a 2.5v 5% or 3.3v 10% power supply, and is guaranteed over the full industrial temperature range (?40c to +85c). the delay varies in discrete steps based on a control word. the control word is 10-bits long and controls the delay in 10ps increments. the eleventh bit is d[10] and is used to simultaneously cascade the sy89295u which allows for a larger delay range. in addition, the input pins in and /in default to an equivalent low state when left floating. further, for maximum flexib ility, the control register interface accepts cmos or ttl level signals. for applications that require an analog delay input, see the sy89296l which is a programmable delay chip with fine tune control. the sy89295u and sy89296u are part of micrel?s high-speed, precision edge ? product line. data sheets and support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? precision lvpecl programmable delay line ? guaranteed ac performance over temperature and voltage: ? >1.5ghz f max ? <160ps rise/fall times ? low-jitter design: ? <10ps pp total jitter ? <2ps rms cycle-to-cycle jitter ? <1ps rms random jitter ? programmable delay range: 3.2ns to 14.8ns in 10ps increments ? increased monotonicity over the mic100ep195 ? 10ps inl ? v bb output reference voltage ? parallel inputs accepts lvpecl or cmos/lvttl ? low voltage operation: 2.5v 5% and 3.3v 10% ? industrial ?40c to +85c temperature range ? available in 32-pin (5mm 5mm) mlf ? and 32-pin tqfp packages applications ? clock de-skewing ? timing adjustments ? aperture centering march 2011 m9999-032511 hbwhelp@micrel.com or (408) 955-1690
micrel, inc. sy89295u march 2011 2 m9999-032511 hbwhelp@micrel.com ordering information (1) part number package type operating range package marking lead finish sy89295umi mlf-32 industrial sy89295u sn-pb sy89295umi tr (2) mlf-32 industrial sy89295u sn-pb sy89295uti t32-1 industrial sy89295u sn-pb sy89295utitr (2) t32-1 industrial sy89295u sn-pb sy89295umg (3) mlf-32 industrial sy89295u with pb-free bar-line indicator pb-free nipd au sy89295umgtr (2, 3) mlf-32 industrial sy89295u with pb-free bar-line indicator pb-free nipd au sy89295utg (3) t32-1 industrial sy89295u with pb-free bar-line indicator pb-free nipd au sy89295utgtr (2, 3) t32-1 industrial sy89295u with pb-free bar-line indicator pb-free nipd au notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. pin configuration 32-pin mlf? (mlf-32) 32-pin tqfp (t32-1) or (408) 955-1690
micrel, inc. sy89295u march 2011 3 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 truth tables input/output inputs outputs in /in out /out 0 1 0 1 1 0 1 0 digital control latch len latch action 0 pass through d[10:0] 1 latched input enable /en q, /q 0 in, /in delayed 1 latched d[10:0]
micrel, inc. sy89295u march 2011 4 m9999-032511 hbwhelp@micrel.com functional block diagram sy89295u block diagram or (408) 955-1690
micrel, inc. sy89295u march 2011 5 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 d[9:0] cmos, ecl, or ttl control bits: these control signals adjust the delay from in to q. see ?ac electrical characteristics? for delay valu es. in addition, see ?interface applications? section which illustrates the proper interfac ing techniques for different logic standards. d[9:0] contains pull-downs an d defaults low when left floating. d0 (lsb), and d9 (msb). see ?typical operating characteristics? for delay information. 3 d10 cmos, ecl, or ttl control bit: this bit is used to cascade devices for an extended delay range. in addition, it drives cascad e, and /cascade. further, d[10] contains a pull-down and defaults low when left floating. 4, 5 in, /in lvpecl/ecl signal input: input signal to be delayed. in contains a 75ky pull-down and will default to a logic low if left floating. 6 vbb (1) reference voltage output: when using a single-ended input signal source to in or /in, connect the unused input of the differential pair to this pin. this pin can also be used to re-bias ac-coupled inputs to in and /in. when used, de-couple to v cc using a 0.01f capacitor, otherwise leave floating if not used. maximum sink/source is 0.5ma. reference voltage output: connect this pin to v cf when d[9:0], and d[10] is ecl.. logic standard v cf connects to: lvpecl v ef , (1) cmos no connect 7 vef ttl 1.5v source 8 vcf reference voltage input: the voltage driven on v cf sets the logic tran sition threshold for d[9:0], and d[10]. 9, 24, 28 gnd, exposed pad (2) negative supply: for mlf ? package, exposed pad must be connected to a ground plane that is the same potent ial as the ground pin. 10 len ecl control input: when high latches the d[ 9:0] and d[10] bits. w hen low, the d[9:0] and d[10] latches are transparent. 11 setmin ecl control input: when high, d[9:0] register s are reset. when low, the delay is set by setmax or d[9:0] and d[10]. setmin contains a pull-down and defaults low when left floating. 12 setmax ecl control input: when setmax is set high and setmin is set low, d[9:0] = 1111111111. when setmax is low, the delay is set by setmin or d[9:0] and d[10]. setmax contains a pull-down and defaults low when left floating. 13, 18, 19, 22 vcc positive power supply: bypas s with 0.1f and 0.01f low esr capacitors. 14, 15 /cascade, cascade lvpecl differential output: the outputs are used when cascading two or more sy89295u to extend the delay range. 16 /en lvpecl single-ended control input: when low, q is delayed from in. when high, q is a differential low. /en contains a pull- down and defaults low when left floating. 20, 21 /q, q lvpecl differential output: q is a delayed version of in. always terminate the output with 50 ? to v cc ? 2v. see ?output interfac e applications? section. 17 nc no connect. notes: 1. single-ended operation is only functional at 3.3v. 2. mlf ? package only.
micrel, inc. sy89295u march 2011 6 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ................................... ?0.5v to +4.0v input voltage (v in ) .......................................... ?0.5v to v cc lvpecl output current (i out ) continuous............................................................50ma surge ..................................................................100ma lead temperature (solderi ng, 20 sec.).................... +260c storage temperature range (t s )............. ?65c to +150c operating ratings (2) supply voltage (v cc ) ............................... +2.375v to +3.6v ambient temperature (t a ).......................... ?40c to +85c package thermal resistance (3) mlf ? ( ja ) still-air ............................................................................... 35c/w mlf ? ( jb ) junction-to-board .......................................................... 28c/w tqfp ( ja ) still-air ............................................................................... 28c/w tqfp ( jb ) junction-to-board .......................................................... 20c/w dc electrical characteristics (4) t a = ?40c to +85c, unless noted. symbol parameter condition min. typ. max. units v cc = 2.5v 2.375 2.5 2.625 v cc power supply v cc = 3.3v 3 3.3 3.6 v i ee power supply current no load, max. v cc 220 ma v in input voltage swing (in, /in ) see figure 1a. 150 1200 mv v diff_in differential input voltage swing (in, /in) see figure 1b. 300 2400 mv v ihcmr input high common mode range in, /in v ee + 1.2 v cc v v cc = 3.3v, t a = ?40c to 85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ih input high voltage (in, /in) 2.075 2.420 v v il input low high voltage (i n, /in) 1.355 1.675 v v bb output voltage refer ence 1.775 1.875 1.975 v v ef mode connection 1.9 2.0 2.1 v v cf input select volt age 1.55 1.65 1.75 v notes: 1. permanent device damage may occur if ?absolute maximum ratings? are exceeded. this is a st ress rating only and functional op eration is not implied at conditions other than those detailed in the operational sections of this data sheet. ex posure to ?absolute maximum rating? cond itions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. thermal performance on mlf ? packages assumes exposed pad is soldered (or equival ent) to the device most negative potential (gnd). 4. the circuit is designed to meet the dc specifications shown in the table above after thermal equilibrium has been establishe d. input and output parameters vary 1:1 with v cc , with the exception of v cf .
micrel, inc. sy89295u march 2011 7 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 dc electrical characteristics (4) (continued) v cc = 2.5v, t a = ?40c to 85c, unless otherwise stated. symbol parameter condition min. typ. max. units v ih input high voltage (in, /in) 1.275 1.62 v v il input low high voltage (i n, /in) 0.555 0.875 v v bb output voltage refer ence 1.175 1.075 0.975 v v ef mode connection 1.10 1.20 1.30 v v cf input select volt age 1.15 1.25 1.35 v lvpecl outputs dc electrical characteristics (4) v cc = 3.3v; r load = 50 ? to v cc ? 2v; t a = ?40c to +85c, unless noted. symbol parameter condition min. typ. max. units v oh output high voltage ( q, /q) 2.155 2.280 2.405 v v ol output low voltage ( q, /q) 1.355 1.480 1.605 v v out output voltage swing (q, /q) see figure 1a. 550 800 mv v diff_out differential output voltage swing (q, /q) see figure 1b. 1.1 1.6 v lvpecl outputs dc electrical characteristics (5) v cc = 2.5v; r load = 50 ? to v cc ? 2v; t a = ?40c to +85c, unless noted. symbol parameter condition min. typ. max. units v cc output high voltage ( q, /q) 1.355 1.480 1.605 v i ee output low voltage ( q, /q) 0.555 0.68 0.805 v v in output voltage swing (q, /q) see figure 1a. 550 800 mv v diff_out differential output voltage swing (q, /q) see figure 1b. 1.1 1.6 v lvttl/cmos dc electri cal characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = ?40c to +85c, unless noted. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current 40 a i il input low current ? 300 a notes: 5. the circuit is designed to meet the dc specifications shown in the table above after thermal equilibrium has been establishe d. v oh and v ol parameters vary 1:1 with v cc . 6. the circuit is designed to meet the dc specifications shown in the table above after thermal equilibrium has been establishe d.
micrel, inc. sy89295u march 2011 8 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (7) t a = ?40c to +85c, unless noted. symbol parameter condition min. typ. max. units f max maximum operating frequency clock v out 400mv 1.5 ghz t pd propagation delay in to q; d[0?10]=0 in to q; d[0?10]=1023 /en to q: d[0?10]=0 d10 to cascade 3200 11500 3400 350 4200 14800 4400 670 ps t range programmable range t pd (max.) ? t pd (min) 8300 ps t skew duty cycle skew t phl ? t plh note 8 25 ps t step delay d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high d9 high d0-d9 high 10 15 35 70 145 290 575 1150 2300 4610 9220 ps inl integral non-linearity note 9 10 ps t s setup time d to len d to in /en to in note 10 note 11 200 350 300 ps t h hold time len to d in to /en note 12 200 400 ps notes : 7. high-frequency ac electricals are guar anteed by design and characterization. 8. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of t he output. 9. inl (integral non-linearity) is defined from its corresponding point on the ideal delay versus d[9:0] curve as the deviation from its ideal delay. the maximum difference is the inl. theoretical ideal linearity (til) = (measured maximum del ay ? measured minimum delay) 1024. in l = measured delay ? measured minimum delay + (step number til). 10. this setup time defines the amount of time prior to the input signal. the delay tap of the device must be set. 11. this setup time defines the amount of the time that /en mu st be asserted prior to the next transition of in, /in to prevent an output response greater than 75mv to the in, /in transition. 12. hold time is the minimum time that /en must remain asse rted after a negative going in or a positive going /in to prevent an output response greater than 75mv to the in, /in transition.
micrel, inc. sy89295u march 2011 9 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (7) t a = ?40c to +85c, unless noted. symbol parameter condition min. typ. max. units t r release time /en to in setmax to len setmin to len 500 500 450 ps t jitter cycle-to-cycle jitter total jitter random jitter note 13 note 14 note 15 2 10 1 ps rms ps pp ps rms t r , t f output rise/fall time 20% to 80% (q) 20% to 80% (cascade) 50 90 85 160 300 ps duty cycle 45 55 % notes : 13. cycle-to-cycle jitter definition: the variation of periods between adjacent cycles over a random sample of adjacent cycle p airs. t jitter_cc = t n ? t n +1, where t is the time between rising edges of the output signal. 14. total jitter definition: with an ideal clock input, no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to- peak jitter value. 15. random jitter definition: jitter that is characterized by a gaussian distri bution, unbounded and is quantified by its stand ard deviation and mean. random jitter is measured with a k28.7 comma defect pattern, measured at 1.5gbps.
micrel, inc. sy89295u march 2011 10 m9999-032511 hbwhelp@micrel.com typical operating characteristics v cc = 3.3v, gnd = 0, d in = 100mv, t a = 25oc, unless otherwise stated. or (408) 955-1690
micrel, inc. sy89295u march 2011 11 m9999-032511 hbwhelp@micrel.com timing diagrams single-ended and di fferential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing input and output stages figure 2a. differential input stage figure 2b. single-ended input stage figure 3. lvpecl output stage or (408) 955-1690
micrel, inc. sy89295u march 2011 12 m9999-032511 hbwhelp@micrel.com output interface applications figure 4. parallel termination figure 5. y-termination figure 6. terminating unused i/o or (408) 955-1690
micrel, inc. sy89295u march 2011 13 m9999-032511 hbwhelp@micrel.com or (408) 955-1690 applications information for best performance, use good high-frequency layout techniques, filter v cc supplies, and keep ground connections short. use multiple vias where possible. also, use controlled impedance transmission lines to interface with the sy89295u data inputs and outputs. v bb reference the vbb pin is an internally generated reference and is available for use only by the sy89295u. when unused, this pin should be left unconnected. two common uses for v bb are to handle a single-ended pecl input, and to re-bias inputs for ac-coupling applications. if in and /in are driven by a single-ended output, v bb is used to bias the unused input. please refer to figure 10. the pecl signal driving the sy89295u may optionally be inverted in this case. when the signal is ac-coupled, v bb is used, as shown in figure 13, to re-bias in and /in. this ensures that sy89295u inputs are within acceptable common mode range. in all cases, v bb current sinking or sourcing must be limited to 0.5ma or less. setting d input logic thresholds in all designs where the sy89295u gnd supply is at zero volts, the d inputs can accommodate cmos and ttl level signals, as well as pecl or lvpecl. figures 11, 12 and 14 show how to connect v cf and v ef for all possible cases. cascading two or more sy89295u may be cascaded in order to extend the range of delays pe rmitted. each additional sy89295u adds about 3.2ns to the minimum delay and adds another 10240ps to the delay range. internal cascade circuitry has been included in the sy89295u. using this internal circuitry, the sy89295u may be cascaded without any external gating. examples of cascading 2, 3, or 4 sy89295u appear in figures 7, 8, and 9.
micrel, inc. sy89295u march 2011 14 m9999-032511 hbwhelp@micrel.com figure 7. cascading two sy89295u figure 8. cascading three sy89295u figure 8. cascading four sy89295u or (408) 955-1690
micrel, inc. sy89295u march 2011 15 m9999-032511 hbwhelp@micrel.com interface applications figure 10. interfacing to a single-ended lvpecl signal figure 11. v cf /v ef biasing for lvpecl control (d) input figure 12. v cf /v ef biasing for cmos (d) input figure 13. re-biasing an ac-coupled signal figure 14. v cf /v ef biasing for lvttl control (d) input related product and su pport documentation part number function datasheet link sy89295u 2.5/3.3v 1.5ghz precision lvpecl programmable delay www.micrel.com/product-info/products/sy89295u.shtml sy89296u 2.5/3.3v 1.5ghz precision lvpecl programmable delay with fine tune control www.micrel.com/product-info/products/sy89296u.shtml 16-mlf manufacturing guidelines exposed pad application note www.amkor.com/products/not es_papers/mlf_appnote_0902.pdf hbw solutions http://www.micrel.com/product-info/as/solutions.shtml or (408) 955-1690
micrel, inc. sy89295u march 2011 16 m9999-032511 hbwhelp@micrel.com package information pcb thermal consideration for 32-pin mlf ? package (always solder, or equivalent, the exposed pad to the pcb) package notes: 1. package meets level 2 qualifications 2. all parts are dry-packed before shipment. 3. exposed pads must be soldered to a ground for proper thermal management. 32-pin mlf ? (mlf-32) or (408) 955-1690
micrel, inc. sy89295u march 2011 17 m9999-032511 hbwhelp@micrel.com package information (continued) 32-pin tqfp (t32-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical impla into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. can nt ? 2006 micrel, incorporated. or (408) 955-1690

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